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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD72874
IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER
The PD72874 is the LSI that integrated OHCI-Link and PHY function into a single chip. The PD72874 complies with the 1394 OHCI Specification 1.1 and the IEEE Std 1394a-2000 specifications, and works up to 400 Mbps. It makes design so compact for PC and PC card application.
FEATURES
* Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.1 * Compliant with Physical Layer Services as defined in IEEE Std 1394a-2000 * Provides three cable ports at 100/200/400 Mbps * Super Low power consumption for Physical Layer * Compliant with protocol enhancement as defined in IEEE Std1394a-2000 * Modular 32-bit host interface compliant to PCI Specification release 2.2 * Supports PCI-Bus Power Management Interface Specification release 1.1 * Modular 32-bit host interface compliant to Card Bus Specification * Cycle Master and Isochronous Resource Manager capable * Built-in FIFOs for isochronous transmit (2048 bytes), asynchronous transmit (2048 bytes), and receive (3072 bytes) * Supports D0, D1, D2, D3hot * Supports wake up function from D3cold * 32-bit CRC generation and checking for receive/transmit packets * 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported * 32-bit DMA channels for physical memory read/write * Clock generation by 24.576 MHz X'tal * 2-wire Serial EEPROM
TM
interface supported
* Separate power supply Link and PHY * Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1)
ORDERING INFORMATION
Part number Package 120-pin plastic TQFP (Fine pitch) (14 x 14)
PD72874GC-YEB
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S15306EJ2V0DS00 (2nd edition) Date Published April 2002 NS CP (K) Printed in Japan
The mark
shows major revised points.
2001
PD72874
FirewardenTM ROADMAP
Firewarden Series
OHCI Link PD72862 IEEE1394-1995 Core Development
1-Chip OHCI+PHY PD72872 1-Chip OHCI+PHY PD72870A, 72870B
1-Chip OHCI 1.1+PHY PD72874 1-Chip OHCI 1.1+PHY PD72873
OHCI Link PD72861 OHCI Link PD72860
1-Chip OHCI+PHY PD72870
Link Core
2
Preliminary Data Sheet S15306EJ2V0DS
GND
GND
BLOCK DIAGRAMS
PCI_VDD P_AVDD P_DVDD PC0 PC1 PC2
L_VDD
LINK BLOCK
IT FIFO
PHY BLOCK
Cable Port0
PCLK PRST RSMRST AT FIFO Link Core State Machine Logic Arbitration and Control State Machine Logic
PCI Interface I/O
TpA0p TpA0n TpB0p TpB0n
Cable Port1
TpA1p TpA1n TpB1p TpB1n
PCI Controller PHY Interface CSR Comand FIFO DMA Controller ROM Interface I/O Register Link Interface
IR FIFO
Cable Port2
TpA2p TpA2n TpB2p TpB2n Voltage and Current Generator Receive Data Decoder and Retimer TpBias0 TpBias1 TpBias2 R0 R1 XI XO Transmit Data Encoder
REQ GNT FRAME CBE0 to CBE3 IRDY DEVSEL TRDY IDSEL STOP INTA AD0 to AD31 PAR PERR SERR CLKRUN
Preliminary Data Sheet S15306EJ2V0DS
PME
D3CSUP
Power Management Controller
CARD_ON
PCI Configuration Register
Cable Power Status
Crystal Oscillator PLL System and Transmit Clock Generator
P_RESET
CPS
GROM_EN GROM_SCL GROM_SDA
PD72874
3
PD72874
PIN CONFIGURATION (TOP VIEW)
* 120-pin plastic TQFP (Fine pitch) (14 x 14)
PD72874GC-YEB
GND CARD_ON GROM_EN GROM_SCL GROM_SDA IC(L) D3CSUP GND P_AVDD TpBias2 TpA2p TpA2n TpB2p TpB2n GND TpA1p TpA1n TpB1p TpB1n TpA0p TpA0n TpB0p TpB0n TpBias1 TpBias0 P_AVDD GND CPS RI1 RI0 L_VDD CLKRUN PME INTA PRST PCLK GNT REQ AD31 AD30 GND AD29 AD28 L_VDD AD27 AD26 AD25 AD24 PCI_VDD GND CBE3 IDSEL AD23 AD22 L_VDD AD21 AD20 AD19 AD18 GND 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P_AVDD GND XO XI P_AVDD IC(N) GND GND P_DVDD P_RESET IC(L) P_DVDD IC(L) IC(L) IC(L) IC(H) RSMRST P_DVDD PC2 PC1 PC0 GND AD0 AD1 AD2 AD3 L_VDD AD4 AD5 GND
4
L_VDD AD17 AD16 CBE2 FRAME IRDY TRDY GND DEVSEL STOP PERR SERR L_VDD PAR CBE1 GND AD15 AD14 AD13 AD12 L_VDD AD11 AD10 GND AD9 AD8 CBE0 AD7 AD6 PCI_VDD
Preliminary Data Sheet S15306EJ2V0DS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
PD72874
PIN NAME
AD0 to AD31 : PCI Multiplexed Address and Data CARD_ON : PCI/Card Select CBE0 to CBE3 CLKRUN CPS D3CSUP DEVSEL FRAME GND GNT : PCICLK Running : Cable Power Status Input : D3cold Support : Device Select : Cycle Frame : GND : Bus_master Grant : Command/Byte Enables
P_AVDD P_DVDD P_RESET REQ RI0 RI1 RSMRST SERR STOP TpA0n TpA0p TpA1n TpA1p TpA2n TpA2p TpB0n TpB0p TpB1n TpB1p TpB2n TpB2p TpBias0 TpBias1 TpBias2 TRDY XI XO
: PHY Analog VDD : PHY Digital VDD : PHY Power on Reset Input : Bus_master Request : Resistor0 for Reference Current Setting : Resistor1 for Reference Current Setting : Resume Reset : System Error : PCI Stop : Port-1 Twisted Pair A Negative Input/Output : Port-1 Twisted Pair A Positive Input/Output : Port-2 Twisted Pair A Negative Input/Output : Port-2 Twisted Pair A Positive Input/Output : Port-3 Twisted Pair A Negative Input/Output : Port-3 Twisted Pair A Positive Input/Output : Port-1 Twisted Pair B Negative Input/Output : Port-1 Twisted Pair B Positive Input/Output : Port-2 Twisted Pair B Negative Input/Output : Port-2 Twisted Pair B Positive Input/Output : Port-3 Twisted Pair B Negative Input/Output : Port-3 Twisted Pair B Positive Input/Output : Port-1 Twisted Pair Bias Voltage Output : Port-2 Twisted Pair Bias Voltage Output : Port-3 Twisted Pair Bias Voltage Output : Target Ready : X'tal XI : X'tal XO
GROM_EN : Serial EEPROM Enable GROM_SCL : Serial EEPROM Clock Output GROM_SDA : Serial EEPROM Data Input / Output IC(H) IC(L) IC(N) IDSEL INTA IRDY L_VDD PAR PC0 to PC2 PCI_VDD PCLK PERR PME PRST : Internally Connected (High Clamped) : Internally Connected (Low Clamped) : Internally Connected (Open) : ID Select : Interrupt : Initiator Ready : VDD for Link Digital Core and Link I/Os : Parity : Power Class Input : VDD for PCI I/Os : PCI Clock : Parity Error : PME Output : Reset
Preliminary Data Sheet S15306EJ2V0DS
5
PD72874
CONTENTS 1. PIN 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 FUNCTIONS..................................................................................................................................... 8 PCI/Cardbus Interface Signals: (52 pins) ...................................................................................... 8 PHY Signals: (20 pins) .................................................................................................................. 10 PHY Control Signals: (4 pins)....................................................................................................... 10 PCI/Cardbus Select Signal: (1 pin)............................................................................................... 10 Serial ROM Interface Signals: (3 pins)......................................................................................... 11 D3cold Wake Up Function Signals: (2 pins) ............................................................................... 11 IC: (7 pins) ...................................................................................................................................... 11 VDD................................................................................................................................................... 12 GND................................................................................................................................................. 12
2. PHY REGISTERS................................................................................................................................... 13 2.1 Complete Structure for PHY Registers........................................................................................ 13 2.2 Port Status Page (Page 000)......................................................................................................... 16 2.3 Vendor ID Page (Page 001) ........................................................................................................... 17 2.4 Vendor Dependent Page (Page 111 : Port_select 0001) ............................................................ 17 3. CONFIGURATION REGISTERS .......................................................................................................... 18 3.1 PCI Bus Mode Configuration Register (CARD_ON = Low)........................................................ 18
3.1.1 Offset_00 3.1.2 Offset_02 3.1.3 Offset_04 3.1.4 Offset_06 3.1.5 Offset_08 3.1.6 Offset_09 3.1.7 Offset_0C 3.1.8 Offset_0D 3.1.9 Offset_0E 3.1.11 Offset_10 3.1.12 Offset_2C 3.1.13 Offset_2E 3.1.14 Offset_34 3.1.15 Offset_3C 3.1.16 Offset_3D 3.1.17 Offset_3E 3.1.18 Offset_3F 3.1.19 Offset_40 3.1.20 Offset_60 3.1.21 Offset_62 3.1.22 Offset_64 3.2.1 Offset_14/18 3.2.2 Offset_28 3.2.3 Offset_80 Vendor ID Register ........................................................................................................... 19 Device ID Register............................................................................................................ 19 Command Register ........................................................................................................... 19 Status Register ................................................................................................................. 20 Revision ID Register ......................................................................................................... 21 Class Code Register......................................................................................................... 21 Cache Line Size Register................................................................................................. 21 Latency Timer Register .................................................................................................... 21 Header Type Register ...................................................................................................... 21 Base Address 0 Register ................................................................................................ 22 Subsystem Vendor ID Register ...................................................................................... 22 Subsystem ID Register................................................................................................... 22 Cap_Ptr Register ............................................................................................................ 22 Interrupt Line Register.................................................................................................... 22 Interrupt Pin Register ..................................................................................................... 23 Min_Gnt Register ........................................................................................................... 23 Max_Lat Register ........................................................................................................... 23 PCI_OHCI_Control Register ........................................................................................... 23 Cap_ID & Next_Item_Ptr Register .................................................................................. 23 Power Management Capabilities Register...................................................................... 24 Power Management Control/Status Register.................................................................. 25 Base Address 1/2 Register (Cardbus Status Registers).............................................. 27
3.1.10 Offset_0F BIST Register .................................................................................................................. 21
3.2 CardBus Mode Configuration Register (CARD_ON = High)...................................................... 26
Cardbus CIS Pointer......................................................................................................... 28 CIS Area ........................................................................................................................... 28
6
Preliminary Data Sheet S15306EJ2V0DS
PD72874
4. PHY FUNCTION.................................................................................................................................... 29 4.1 Cable Interface............................................................................................................................... 29
4.1.1 Connections ......................................................................................................................................... 29 4.1.2 Cable Interface Circuit.......................................................................................................................... 30 4.1.3 CPS ...................................................................................................................................................... 30 4.1.4 Unused Ports........................................................................................................................................ 30
4.2 PLL and Crystal Oscillation Circuit ............................................................................................. 30
4.2.1 Crystal Oscillation Circuit ..................................................................................................................... 30 4.2.2 PLL ....................................................................................................................................................... 30
4.3 PC0 to PC2 ..................................................................................................................................... 30 4.4 P_RESET ........................................................................................................................................ 30 4.5 RI0, RI1 ........................................................................................................................................... 30 5. ELECTRICAL SPECIFICATIONS......................................................................................................... 31 6. PACKAGE DRAWING .......................................................................................................................... 34 7. RECOMMENDED SOLDERING CONDITIONS................................................................................... 35
Preliminary Data Sheet S15306EJ2V0DS
7
PD72874
1. PIN FUNCTIONS 1.1 PCI/Cardbus Interface Signals: (52 pins)
(1/2)
Name PAR I/O I/O 44 Pin No. IOL
PCI/Cardbus
Volts(V) 5/3.3
Function Parity is even parity across AD0 to AD31 and CBE0 to CBE3. It is an input when AD0 to AD31 is an input; it is an output when AD0 to AD31 is an output.
Block * Link
AD0 to AD31
I/O
9, 10, 12, 13, 15 to18, 23, 24, 26 to 29, 32, 33, 47 to 50, 52, 53, 55, 56, 58, 59, 62, 63, 65 to 68
PCI/Cardbus
5/3.3
PCI Multiplexed Address and Data
Link
CBE0 to CBE3 FRAME
I/O
21, 34, 45, 57
-
5/3.3
Command/Byte Enables are multiplexed bus commands & byte enables.
Link
I/O
35
PCI/Cardbus
5/3.3
Frame is asserted by the initiator to indicate the cycle beginning and is kept asserted during the burst cycle. If Cardbus mode (CARD_ON = 1), this pin should be pulled up to VDD.
Link
TRDY
I/O
37
PCI/Cardbus
5/3.3
Target Ready indicates that the current data phase of the transaction is ready to be completed.
Link
IRDY
I/O
36
PCI/Cardbus
5/3.3
Initiator Ready indicates that the current bus master is ready to complete the current data phase. During a write, its assertion indicates that the initiator is driving valid data onto the data bus. During a read, its assertion indicates that the initiator is ready to accept data from the currentlyaddressed target.
Link
REQ
O
8
PCI/Cardbus
5/3.3
Bus_master Request indicates to the bus arbiter that this device wants to become a bus master.
Link
GNT
I
7
-
5/3.3
Bus_master Grant indicates to this device that access to the bus has been granted.
Link
IDSEL
I
22
-
5/3.3
Initialization Device Select is used as chip select for configuration read/write transaction during the phase of device initialization. If Cardbus mode (CARD_ON = 1), this pin should be pulled up to VDD.
Link
DEVSEL
I/O
39
PCI/Cardbus
5/3.3
Device Select when actively driven, indicates that the driving device has decoded its address as the target of the current access.
Link
STOP
I/O
40
PCI/Cardbus
5/3.3
PCI Stop when actively driven, indicates that the target is requesting the current bus master to stop the transaction.
Link
PME
O
3
PCI/Cardbus
5/3.3
PME Output for power management event.
Link
Remark *: If the Link pin is pulled up, it should be connected to L_VDD.
8
Preliminary Data Sheet S15306EJ2V0DS
PD72874
(2/2)
Name CLKRUN I/O I/O 2 Pin No. IOL
PCI/Cardbus
Volts(V) 5/3.3
Function PCICLK Running as input, to determine the status of PCLK; as output, to request starting or speeding up clock.
Block * Link
INTA PERR
O I/O
4 41
PCI/Cardbus PCI/Cardbus
5/3.3 5/3.3
Interrupt the PCI interrupt request A. Parity Error is used for reporting data parity errors during all PCI transactions, except a special cycle. It is an output when AD0 to AD31 and PAR are both inputs. It is an input when AD0 to AD31 and PAR are both outputs.
Link Link
SERR
O
42
PCI/Cardbus
5/3.3
System Error is used for reporting address parity errors, data parity errors during the special cycle, or any other system error where the effect can be catastrophic. When reporting address parity errors, it is an output.
Link
PRST PCLK
I I
5 6
-
5/3.3 5/3.3
Reset PCI reset PCI Clock 33 MHz system bus clock.
Link Link
Remark *: If the Link pin is pulled up, it should be connected to L_VDD.
Preliminary Data Sheet S15306EJ2V0DS
9
PD72874
1.2 PHY Signals: (20 pins)
Name TpA0p TpA0n TpB0p TpB0n TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n CPS TpBias0 TpBias1 TpBias2 RI0 RI1 XI XO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O O I O 101 100 99 98 105 104 103 102 110 109 108 107 93 96 97 111 91 92 87 88 Pin No. IOL Volts(V) Function Port-1 Twisted Pair A Positive Input/Output
Note 1
Block * PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Digital
Note 1 Note 1
Port-1 Twisted Pair A Negative Input/Output Note 1 Port-1 Twisted Pair B Positive Input/Output Note 1 Port-1 Twisted Pair B Negative Input/Output
Note 1
Port-2 Twisted Pair A Positive Input/Output Note 1 Port-2 Twisted Pair A Negative Input/Output Note 1 Port-2 Twisted Pair B Positive Input/Output
Note 1 Note 1
Port-2 Twisted Pair B Negative Input/Output
Port-3 Twisted Pair A Positive Input/Output Note 1 Port-3 Twisted Pair A Negative Input/Output Note 1 Port-3 Twisted Pair B Positive Input/Output
Note 1
Port-3 Twisted Pair B Negative Input/Output Note 1 Cable Power Status Input Note2 Port-1 Twisted Pair Bias Voltage Output Port-2 Twisted Pair Bias Voltage Output
PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog
Port-3 Twisted Pair Bias Voltage Output Note 1 Resistor0 for Reference Current Setting Resistor1 for Reference Current Setting X'tal XI X'tal XO
Note 3 Note 3
Notes 1. If unused port, please refer to 4.1.4 Unused Ports. 2. Please refer to 4.1.3 CPS. 3. Please refer to 4.5 RI0, RI1. Remark *: If the PHY Digital pin is pulled up, it should be connected to P_DVDD. If the PHY Analog pin is pulled up, it should be connected to P_AVDD.
1.3 PHY Control Signals: (4 pins)
Name PC0 to PC2 P_RESET I/O I I Pin No. 70 to 72 81 IOL Volts(V) 3.3 Power Class Input Function
Note 1
Block * PHY Digital PHY Digital
PHY Power on Reset Input Note 2
Notes 1. Please refer to 4.3 PC0 to PC2. 2. Please refer to 4.4 P_RESET. Remark *: If the PHY Digital pin is pulled up, it should be connected to P_DVDD.
1.4 PCI/Cardbus Select Signal: (1 pin)
Name CARD_ON I/O I 119 Pin No. IOL Volts(V) 3.3 PCI/CardBus Select 1:Cardbus mode 0:PCI bus mode Function Block * Link
Remark *: If the Link pin is pulled up, it should be connected to L_VDD.
10
Preliminary Data Sheet S15306EJ2V0DS
PD72874
1.5 Serial ROM Interface Signals: (3 pins)
Name GROM_SDA GROM_SCL GROM_EN I/O I/O O I 116 117 118 Pin No. IOL 6 mA 6 mA Volts(V) 3.3 3.3 3.3 Function Serial EEPROM Data Input / Output Serial EEPROM Clock Output Serial EEPROM Enable 1: GUID Load enable 0: GUID Load disable Block * Link Link Link
Remark *: If the Link pin is pulled up, it should be connected to L_VDD.
1.6 D3cold Wake Up Function Signals: (2 pins)
Name D3CSUP I/O I 114 Pin No. IOL Volts(V) 5/3.3 D3cold Support 1: D3cold wake up enable 0: D3cold wake up disable RSMRST I 74 5/3.3 Resume Reset D3cold support (114 pin) = `1' As this mode supports D3cold wake up, RSMRST must connect system RSMRST signal. Link Function Block * Link
D3cold support (114 pin) = `0' As this mode is the PD72872 compatible, RSMRST clamp to `1'.
Remark *: If the Link pin is pulled up, it should be connected to L_VDD.
1.7 IC: (7 pins)
Name IC(H) IC(L) IC(N) I/O I I 75 76 to 78, 80, 115 85 Pin No. IOL Volts(V) Function Internally Connected (High clamped) Internally Connected (Low clamped) Internally Connected (Open) Block * Link -
Remark *: If the Link pin is pulled up, it should be connected to L_VDD.
Preliminary Data Sheet S15306EJ2V0DS
11
PD72874
1.8 VDD
Name PCI_VDD L_VDD I/O Pin No. 19, 60 1, 14, 25, 31, 43, 51, 64 IOL Volts(V) 5/3.3 3.3 VDD for PCI I/Os VDD for Link digital Core and Link I/Os To use D3cold wake up function, L_VDD must switch VDD to Vaux when the system suspend. P_DVDD P_AVDD 73, 79, 82 86, 90, 95, 112 3.3 3.3 PHY digital VDD PHY Analog VDD PHY Digital PHY Analog Function Block * Link Link
Remark *: If the Link pin is pulled up, it should be connected to L_VDD. If the PHY Digital pin is pulled up, it should be connected to P_DVDD. If the PHY Analog pin is pulled up, it should be connected to P_AVDD.
1.9 GND
Name GND I/O Pin No. 11, 20, 30, 38, 46, 54, 61, 69, 83, 84, 89, 94, 106, 113, 120 IOL Volts(V) GND Function Block -
12
Preliminary Data Sheet S15306EJ2V0DS
PD72874
2. PHY REGISTERS 2.1 Complete Structure for PHY Registers
Figure 2-1. Complete Structure of PHY Registers
0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Page_select Link_active Watchdog RHB IBR Extended (7) Max_speed Contender ISBR Loop Reserved Reserved Jitter Pwr_fail Timeout Port_event 1 2 Physical_ID Gap_count Total_ports Delay Pwr_class Enab_accel Enab_multi 3 4 5 6 R 7 PS
Reserved Reserved Register0 (page_select) Register1 (page_select) Register2 (page_select) Register3 (page_select) Register4 (page_select) Register5 (page_select) Register6 (page_select) Register7 (page_select) Port_select
Table 2-1. Bit Field Description (1/3)
Field Physical_ID R Size 6 1 R/W R R Reset value 000000 0 Description Physical_ID value selected from Self_ID period. If this bit is 1, the node is root. 1: Root 0: Not root PS 1 R Cable power status. 1: Cable power on 0: Cable power off RHB IBR 1 1 R/W R/W 0 0 Root Hold -off bit. If 1, becomes root at the bus reset. Initiate bus reset. Setting to 1 begins a long bus reset. Long bus reset signal duration: 166 sec. Returns to 0 at the beginning of bus reset. Gap_count 6 R/W 111111 Gap count value. It is updated by the changes of transmitting and receiving the PHY configuration packet Tx/Rx. The value is maintained after first bus reset. After the second bus reset it returns to reset value. Extended 3 R 111 Shows the extended register map.
Preliminary Data Sheet S15306EJ2V0DS
13
PD72874
Table 2-1. Bit Field Description (2/3)
Field Total_ports Size 4 R/W R Reset value 0011 Supported port number. 0011: 3 ports Max_speed 3 R 010 Indicate the maximum speed that this node supports. 010: 98.304, 196.608 and 393.216 Mbps Delay Link_active 4 1 R R/W 0000 1 Indicate worst case repeating delay time. 144 + (Delay x 20) = 144 nsec Link active. 1: Enable 0: Disable The logical AND status of this bit and LPS. State will be referred to "L bit" of Self-ID Packet#0. The LPS is a PHY/Link interface signal and is defined in P1394a-2000. It is an internal signal in the PD72874. Contender 1 R/W 0 Contender. "1" indicate this node support bus manager function. This bit will be referred to "C bit" of Self-ID Packet#0. Jitter Pwr_class 3 3 R R/W 010 See Description The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsec Power class. Please refer to IEEE1394a-2000 [4.3.4.1]. This bit will be referred to Pwr field of Self-ID Packet#0. Watchdog 1 R/W 0 Watchdog Enable. This bit serves two purposes. When set to 1, if any one port does resume, the Port_event bit becomes 1. To determine whether or not an interrupt condition shall be indicated to the link. On condition of LPS = 0 and Watchdog = 0, LKON as interrupt of Loop, Pwr_fail, Timeout is not output. ISBR 1 R/W 0 Initiate short (arbitrated) bus reset. Setting to 1 acquires the bus and begins short bus reset. Short bus reset signal output : 1.3 sec Returns to 0 at the beginning of the bus reset. Loop 1 R/W 0 Loop detection output. 1: Detection Writing 1 to this bit clears it to 0. Writing 0 has no effect. Pwr_fail 1 R/W 1 Power cable disconnect detect. It becomes 1 when there is a change from 1 to 0 in the CPS bit. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Description
14
Preliminary Data Sheet S15306EJ2V0DS
PD72874
Table 2-1. Bit Field Description (3/3)
Field Timeout Size 1 R/W R/W Reset value 0 Description Arbitration state machine time-out. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Port_event 1 R/W 0 Set to 1 when the Int_enable bit in the register map of each port is 1 and there is a change in the ports connected, Bias, Disabled and Fault bits. Set to 1 when the Watchdog bit is 1 and any one port does resume. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Enab_accel 1 R/W 0 Enables arbitration acceleration. Ack-acceleration and Fly-by arbitration are enabled. 1: Enabled 0: Disabled If this bit changes while the bus request is pending, the operation is not guaranteed. Enab_multi 1 R/W 0 Enable multi-speed packet concatenation. Setting this bit to 1 follows multi-speed transmission. When this bit is set to 0,the packet will be transmitted with the same speed as the first packet. Page_select 3 R/W 000 Select page address between 1000 to 1111. 000: Port Status Page 001: Vendor ID Page 111: Vendor Dependent Page Others: Unused Port_select 4 R/W 0000 Port Selection. Selecting 000 (Port Status Page) with the Page_select selects the port. Selecting 111 (Vendor Dependent Page) with the Page_select have to select the Port 1. 0000: Port 0 0001: Port 1 0010: Port 2 Others: Unused Reserved R 000... Reserved. Read as 0.
Preliminary Data Sheet S15306EJ2V0DS
15
PD72874
2.2 Port Status Page (Page 000)
Figure 2-2. Port Status Page
0 1000 1001 1010 1011 1100 1101 1110 1111 AStat Negotiated_speed 1 2 BStat Int_enable 3 4 Child Fault 5 Connected 6 Bias Reserved 7 Disabled
Reserved Reserved Reserved Reserved Reserved Reserved
Table 2-2. Bit Field Description
Field AStat Size 2 R/W R Reset value XX A port status value. 00: invalid, 10: "0" 01: "1", 11: "Z" BStat 2 R XX B port status value. 00: invalid, 10: "0" 01: "1", 11: "Z" Child 1 R Child node status value. 1: Connected to child node 0: Connected to parent node Connected 1 R 0 Connection status value. 1: Connected 0: Disconnected Bias 1 R Bias voltage status value. 1: Bias voltage 0: No bias voltage Disabled 1 R/W See Description Negotiated_ Speed 3 R Shows the maximum data transfer rate of the node connected to this port. 000: 100 Mbps 001: 200 Mbps 010: 400 Mbps Int_enable 1 R/W 0 When set to 1, the Port_event is set to 1 if any of this port's Connected, Bias, Disabled or Fault bits change state. Fault 1 R/W 0 Set to 1 if an error occurs during Suspend/Resume. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Reserved R 000... Reserved. Read as 0. The reset value is set to 0: Enabled. Description
16
Preliminary Data Sheet S15306EJ2V0DS
PD72874
2.3 Vendor ID Page (Page 001)
Figure 2-3. Vendor ID Page
0 1000 1001 1010 1011 1100 1101 1110 1111 Product_ID Vendor_ID 1 2 3 4 5 6 7
Compliance_level Reserved
Table 2-3. Bit Field Description
Field Compliance_level Vendor_ID Product_ID Reserved Size 8 24 24 R/W R R R R 000... Reset value 00000001 00004CH According to IEEE1394a-2000. Company ID Code value, NEC IEEE OUI. Product code. Reserved. Read as 0. Description
2.4 Vendor Dependent Page (Page 111 : Port_select 0001)
Figure 2-4. Vendor Dependent Page
0 1000 1001 1010 1011 1100 1101 1110 1111 Reg_array 1 2 3 4 5 6 7
Table 2-4. Bit Field Description
Field Reg_array Size 64 R/W R/W Reset value 0 Description This register array is possible R/W.
Preliminary Data Sheet S15306EJ2V0DS
17
PD72874
3. CONFIGURATION REGISTERS 3.1 PCI Bus Mode Configuration Register (CARD_ON = Low)
31 24 23 16 15 08 07 00 00H 04H Revision ID Latency Timer Base Address 0 Reserved Reserved Reserved Reserved Reserved Reserved Subsystem ID Reserved Reserved Reserved Max_Lat Min_Gnt Interrupt Pin PCI_OHCI_Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Power Management Capabilities Reserved Reserved Next_Item_Ptr Cap_ID Interrupt Line Cap_Ptr Subsystem Vendor ID Cache Line Size 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H FCH
Device ID Status Class Code BIST Header Type
Vendor ID Command
Power Management Control/Status
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Preliminary Data Sheet S15306EJ2V0DS
PD72874
3.1.1 Offset_00 Vendor ID Register This register identifies the manufacturer of the PD72874. The ID is assigned by the PCI_SIG committee.
Bits 15-0 R/W R Constant value of 1033H. Description
3.1.2 Offset_02 Device ID Register This register identifies the type of the device for the PD72874. The ID is assigned by NEC Corporation.
Bits 15-0 R/W R Constant value of 00F2H. Description
3.1.3 Offset_04
Command Register
The register provides control over the device's ability to generate and respond to PCI cycles.
Bits 0 1 R/W R R/W Description I/O enable Constant value of 0. The PD72874 does not respond to PCI I/O accesses. Memory enable Default value of 1. It defines if the PD72874 responds to PCI memory accesses. This bit should be set to one upon power-up reset. 0: The PD72874 does not respond to PCI memory cycles 1: The PD72874 responds to PCI memory cycles 2 R/W Master enable Default value of 1. It enables the PD72874 as bus-master on the PCI-bus. 0: The PD72874 cannot generate PCI accesses by being a bus-master 1: The PD72874 is capable of acting as a bus-master 3 R Special cycle monitor enable Constant value of 0. The special cycle monitor is always disabled. 4 R/W Memory write and invalidate enable Default value of 0. It enables Memory Write and Invalid Command generation. 0: Memory write must be used 1: The PD72874, when acts as PCI master, can generate the command 5 R VGATM color palette invalidate enable Constant value of 0. VGA color palette invalidate is always disabled. 6 R/W Parity error response Default value of 0. It defines if the PD72874 responds to PERR. 0: Ignore parity error 1: Respond to parity error 7 8 R R/W Stepping enable Constant value of 0. Stepping is always disabled. System error enable Default value of 0. It defines if the PD72874 responds to SERR. 0: Disable system error checking 1: Enable system error checking 9 R Fast back-to-back enable Constant value of 0. Fast back-to-back transactions are only allowed to the same agent. 15-10 R Reserved Constant value of 000000.
Preliminary Data Sheet S15306EJ2V0DS
19
PD72874
3.1.4 Offset_06 Status Register This register tracks the status information of PCI-bus related events which are relevant to the PD72874. "Read" and "Write" are handled somewhat differently.
Bits 3-0 4 6,5 7 R/W R R R R Reserved Constant value of 0000. New capabilities Constant value of 1. It indicates the existence of the Capabilities List. Description
Reserved Constant value of 00. Fast back-to-back capable Constant value of 1. It indicates that the PD72874, as a target, cannot accept fast back-to-back transactions when the transactions are not to the same agent.
8
R/W
Signaled parity error Default value of 0. It indicates the occurrence of any "Data Parity". 0: No parity detected (default) 1: Parity detected
10,9
R
DEVSEL timing Constant value of 01. These bits define the decode timing for DEVSEL. 0: Fast (1 cycle) 1: Medium (2 cycles) 2: Slow (3 cycles) 3: undefined
11
R/W
Signaled target abort Default value of 0. This bit is set by a target device whenever it terminates a transaction with "Target Abort". 0: The PD72874 did not terminate a transaction with Target Abort 1: The PD72874 has terminated a transaction with Target Abort
12
R/W
Received target abort Default value of 0. This bit is set by a master device whenever its transaction is terminated with a "Target Abort". 0: The PD72874 has not received a Target Abort 1: The PD72874 has received a Target Abort from a bus-master
13
R/W
Received master abort
Default value of 0. This bit is set by a master device whenever its
transaction is terminated with "Master Abort". The PD72874 asserts "Master Abort" when a transaction response exceeds the time allocated in the latency timer field. 0: Transaction was not terminated with a Master Abort 1: Transaction has been terminated with a Master Abort 14 R/W Signaled system error Default value of 0. It indicates that the assertion of SERR by the
PD72874.
0: System error was not signaled 1: System error was signaled 15 R/W Received parity error Default value of 0. It indicates the occurrence of any PERR. 0: No parity error was detected 1: Parity error was detected
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Preliminary Data Sheet S15306EJ2V0DS
PD72874
3.1.5 Offset_08 Revision ID Register This register specifies a revision number assigned by NEC Corporation for the PD72874.
Bits 7-0 R/W R Description Default value of 01H. It specifies the silicon revision. It will be incremented for subsequent silicon revisions.
3.1.6 Offset_09 Class Code Register This register identifies the class code, sub-class code, and programming interface of the PD72874.
Bits 7-0 15-8 23-16 R/W R R R Description Constant value of 10H. It specifies an IEEE1394 OHCI-compliant Host Controller. Constant value of 00H. It specifies an "IEEE1394" type. Constant value of 0CH. It specifies a "Serial Bus Controller".
3.1.7 Offset_0C
Cache Line Size Register
This register specifies the system cache line size, which is PC-host system dependent, in units of 32-bit words. The following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. All other values will be recognized as 0, i.e. cache disabled.
Bits 7-0 R/W R/W Default value of 00H. Description
3.1.8 Offset_0D Latency Timer Register This register defines the maximum amount of time that the PD72874 is permitted to retain ownership of the bus after it has acquired bus ownership and initiated a subsequent transaction.
Bits 7-0 R/W R/W Description Default value of 00H. It specifies the number of PCI-bus clocks that the PD72874 may hold the PCI bus as a bus-master.
3.1.9 Offset_0E
Bits 7-0
Header Type Register
R/W R Description Constant value of 00H. It specifies a single function device.
3.1.10 Offset_0F BIST Register
Bits 7-0 R/W R Description Constant value of 00H. It specifies whether the device is capable of Built-in Self Test.
Preliminary Data Sheet S15306EJ2V0DS
21
PD72874
3.1.11 Offset_10 Base Address 0 Register
This register specifies the base memory address for accessing all the "Operation registers" (i.e. control, configuration, and status registers) of the PD72874, while the BIOS is expected to set this value during power-up reset.
Bits 11-0 31-12 R/W R R/W Description Constant value of 000H. These bits are "read-only". -
3.1.12 Offset_2C Subsystem Vendor ID Register This register identifies the subsystem that contains the NEC's PD72874 function. While the ID is assigned by the PCI_SIG committee, the value should be loaded into the register from the external serial ROM after power-up reset. Access to this register through PCI-bus is prohibited.
Bits 15-0 R/W R Default value of 1033H. Description
3.1.13 Offset_2E Subsystem ID Register This register identifies the type of the subsystem that contains the NEC's PD72874 function. While the ID is assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after power-up reset. Access to this register through PCI-bus is prohibited.
Bits 15-0 R/W R Default value of 00F2H. Description
3.1.14 Offset_34 Cap_Ptr Register This register points to a linked list of additional capabilities specific to the PD72874, the NEC's implementation of the 1394 OHCI specification.
Bits 7-0 R/W R Description Constant value of 60H. The value represents an offset into the PD72874's PCI Configuration Space for the location of the first item in the New Capabilities Linked List.
3.1.15 Offset_3C Interrupt Line Register This register provides the interrupt line routing information specific to the PD72874, the NEC's implementation of the 1394 OHCI specification.
Bits 7-0 R/W R/W Description Default value of 00H. It specifies which input of the host system interrupt controller the interrupt pin of the PD72874 is connected to.
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Preliminary Data Sheet S15306EJ2V0DS
PD72874
3.1.16 Offset_3D Interrupt Pin Register This register provides the interrupt line routing information specific to the PD72874, the NEC's implementation of the 1394 OHCI specification.
Bits 7-0 R/W R Description Constant value of 01H. It specifies PCI INTA is used for interrupting the host system.
3.1.17 Offset_3E Min_Gnt Register This register specifies how long of a burst period the PD72874 needs, assuming a clock rate of 33 MHz. Resolution is in units of 1/4 s. The value should be loaded into the register from the external serial EEPROM upon power-up reset, and access to this register through PCI-bus is prohibited.
Bits 7-0 R/W R Description Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.18 Offset_3F Max_Lat Register This register specifies how often the PD72874 needs to gain access to the PCI-bus, assuming a clock rate of 33 MHz. Resolution is in units of 1/4 s. The value should be loaded into the register from the external serial EEPROM after hardware reset, and access to this register through PCI-bus is prohibited.
Bits 7-0 R/W R Description Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.19 Offset_40
PCI_OHCI_Control Register
This register specifies the control bits that are IEEE1394 OHCI specific. Vendor options are not allowed in this register. It is reserved for OHCI use only.
Bits 0 R/W R/W Description PCI global SWAP Default value of 0. When this bit is 1, all quadrates read from and written to the PCI Interface are byte swapped, thus a "PCI Global Swap". PCI addresses for expansion ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not required for motherboard implementations. 31-1 R Reserved Constant value of all 0.
3.1.20 Offset_60
Cap_ID & Next_Item_Ptr Register
The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the Next_Item_Ptr describes the location of the next item in the PD72874's Capability List.
Bits 7-0 R/W R Description Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCI Power Management registers, while the ID value is assigned by the PCI SIG. 15-8 R Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the Link List.
Preliminary Data Sheet S15306EJ2V0DS
23
PD72874
3.1.21 Offset_62 Power Management Capabilities Register
This is a 16-bit read-only register that provides information on the power management capabilities of the PD72874.
Bits 2-0 R/W R Description Version Constant value of 010. The power management registers are implemented as defined in revision 1.1 of PCI Bus Power Management Interface Specification. 3 4 5 8-6 R R R R PME clock Constant value of 0. Reserved Constant value of 0. DSI Constant value of 0. Auxiliary Power Default value of 000. This field reports the Vaux power requirements for the
PD72874. This data is programable from EEPROM.
111 - 375 mA maximum current required for a 3.3 Vaux, 110 - 320 mA maximum current required for a 3.3 Vaux, 101 - 270 mA maximum current required for a 3.3 Vaux, 100 - 220 mA maximum current required for a 3.3 Vaux, 011 - 160 mA maximum current required for a 3.3 Vaux, 010 - 100 mA maximum current required for a 3.3 Vaux, 001 - 55 mA maximum current required for a 3.3 Vaux, 000 - 0 (self powered) 9 10 15-11 R R R D1_support Constant value of 1. The PD72874 supports the D1 Power Management state. D2_support Constant value of 1. The PD72874 supports the D2 Power Management state. PME_support D3SUP = `High' : Constant value of 11111. D3SUP = `Low' : Constant value of 01111. This field indicates the power states in which the PD72874 may assert PME. A value of "0" for any bit indicates that the function is not capable of asserting the PME signal while in that power state. bit (11) - PME_D0. PME can be asserted from D0. bit (12) - PME_D1. PME can be asserted from D1. bit (13) - PME_D2. PME can be asserted from D2. bit (14) - PME_D3hot. PME can be asserted from D3hot. bit (15) - PME_D3cold. PME can be asserted from D3cold.
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Preliminary Data Sheet S15306EJ2V0DS
PD72874
3.1.22 Offset_64 Power Management Control/Status Register This is a 16-bit register that provides control status information of the PD72874.
Bits 1,0 R/W R/W Description PowerState Default value is undefined. This field is used both to determine the current power state of the PD72874 and to set the PD72874 into a new power state. 00: D0 (DMA contexts: ON, Link Layer: ON, PME will be asserted upon INTA being active.) 01: D1 (DMA contexts: OFF, Link Layer: ON, PME will be asserted upon INTA being active) 10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon LinkON being active) 11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon LinkON being active) The LPS is a PHY/Link interface signal and is defined in P1394a-2000. It is an internal signal in the PD72874. 7-2 8 R R/W Reserved Constant value of 000000. PME_En Default value of 0. This field is used to enable the specific power management features of the PD72874. 12-9 14,13 15 R R R/W Data_Select Constant value of 0000. Data_Scale Constant value of 00. PME_Status Default value is undefined. A write of `1' clears this bit, while a write of `0' is ignored.
Preliminary Data Sheet S15306EJ2V0DS
25
PD72874
3.2 CardBus Mode Configuration Register (CARD_ON = High)
31 24 23 16 15 08 07 00 00H 04H Revision ID Latency Timer Base Address 0 Base Address 1 (Cardbus Status Reg) Note Base Address 2 (Cardbus Status Reg) Reserved Reserved Reserved Cardbus CIS Pointer Note Subsystem ID Reserved Reserved Reserved Max_Lat Min_Gnt Interrupt Pin PCI_OHCI_Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Power Management Capabilities Reserved Reserved Reserved Reserved Reserved Reserved Reserved CIS Area Note Next_Item_Ptr Cap_ID Interrupt Line Cap_Ptr Subsystem Vendor ID
Note
Device ID Status Class Code BIST Header Type
Vendor ID Command
08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H FCH
Cache Line Size
Power Management Control/Status
Note Different from PCI Bus Mode Configuration Register.
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Preliminary Data Sheet S15306EJ2V0DS
PD72874
3.2.1 Offset_14/18
Bits 7-0 31-8
Base Address 1/2 Register (Cardbus Status Registers)
R/W R R/W Constant value of 00. Description
(1) Function Event Register (FER) (Base Address 1 (2) + 0H)
Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 14-5 15 31-16 R/W R R/W R General Wake Up Reserved. Read only as `0' Interrupt Reserved. Read only as `0' Description
(2) Function Event Mask Register (FEMR) (Base Address 1 (2) + 4H)
Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 5 6 13-7 14 15 31-16 R/W R R R R/W R/W R General Wake Up Mask BAM. Read only as `0' PWM. Read only as `0' Reserved. Read only as `0' Wake Up Mask Interrupt Reserved. Read only as `0' Description
Preliminary Data Sheet S15306EJ2V0DS
27
PD72874
(3) Function Reset Status Register (FRSR) (Base Address 1 (2) + 8H)
Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 14-5 15 31-16 R/W R R/W R General Wake Up Mask Reserved. Read only as `0' Interrupt Reserved. Read only as `0' Description
(4) Function Force Event Register (FFER) (Base Address 1 (2) + CH)
Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 14-5 15 31-16 R/W R/W R General Wake Up Mask No Use Interrupt Reserved. Read only as `0' Description
3.2.2 Offset_28
Cardbus CIS Pointer
This register specifies start memory address of the Cardbus CIS Area.
Bits 31-0 R/W R Starting Pointer of CIS Area. Constant value of 00000080H. Description
3.2.3 Offset_80 CIS Area The PD72874 supports external Serial ROM (AT24C02 compatible) interface. CIS Area Register can be loaded from external Serial ROM in the CIS area when CARD_ON is 1.
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Preliminary Data Sheet S15306EJ2V0DS
PD72874
4. PHY FUNCTION 4.1 Cable Interface
4.1.1 Connections Figure 4-1. Cable Interface
Connection Detection Current Connection Detection Comparator Common Mode Speed Current driver
+ Driver
TpBias TpAp 7 k 7 k TpAn 56 56 56 56 TpBp 7 k 7 k TpBn Receiver + Arbitration Comparators + + Common Mode Comparator + Connection Detection Current Connection Detection Comparator Driver
Receiver + Arbitration Comparators + + Common Mode Comparators + + -
1 F
0.01 F
5.1 k
270 pF
Common Mode Speed Current Driver
TpBias TpBp Driver 7 k 7 k TpBn Receiver + Arbitration Comparators + + Common Mode Comparator + 270 pF 5.1 k 0.01 F 1 F 56 56 56 56 TpAp 7 k 7 k TpAn
+ Driver
Receiver + Arbitration Comparators + + Common Mode Comparators + + -
Preliminary Data Sheet S15306EJ2V0DS
29
PD72874
4.1.2 Cable Interface Circuit Each port is configured with two twisted-pairs of TpA and TpB. TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables. During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is encoded, converted from parallel to serial and transmitted. While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel after synchronization by SCLK Note, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate of 100/200/400 Mbps. The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of the 1394 bus is transmitted to the state machine in the LSI. Note The SCLK is a PHY/Link interface signal and is defined in P1394a-2000. It is an internal signal in the PD72874. 4.1.3 CPS Connect an external resistor of 390 k between the CPS pin and the power cable, and an external resistor of 100 k between the CPS pin and the GND to monitor the power of the power cable. If the cable power falls under 7.5 V there is an indication to the Link layer that the power has failed. 4.1.4 Unused Ports TpAp, TpAn : Not connected TpBp, TpBn : AGND TpBias : Not connected
4.2 PLL and Crystal Oscillation Circuit
4.2.1 Crystal Oscillation Circuit To supply the clock of 24.576 MHz 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm. 4.2.2 PLL The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).
4.3 PC0 to PC2
The PC0 to PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can be changed with software through the Link layer; this pin sets the initial value during Power-on Reset. Use a pull-up or pull-down resistor of 1 k based on the application.
4.4 P_RESET
Connect an external capacitor of 0.1 F between the pins P_RESET and GND. If the voltage drops below 0 V, a reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register.
4.5 RI0, RI1
Connect an external resistor of 9.1 k 0.5 % to limit the LSI's current.
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Preliminary Data Sheet S15306EJ2V0DS
PD72874
5. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Symbol VDD VI LVTTL @ (VI < 0.5 V + VDD) PCI @ (VI < 3.0 V + VDD) Output voltage VO LVTTL @ (VO < 0.5 V + VDD) PCI @ (VO < 3.0 V + VDD) Operating ambient temperature Storage temperature TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 -0.5 to +6.6 -0.5 to +4.6 -0.5 to +6.6 0 to +70 -65 to +150 Unit V V V V V C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Ranges
Parameter Power supply voltage Symbol VDD Condition Used to clamp reflection on PCI bus. Rating 4.5 to 5.5 3.0 to 3.6 Operating ambient temperature TA 0 to +70 Unit V V C
Preliminary Data Sheet S15306EJ2V0DS
31
PD72874
DC Characteristics (VDD = 3.3 V 10 %, VSS = 0 V, TA = 0 to +70C)
Parameter High-level input voltage Low-level input voltage High-level output current Symbol VIH VIL IOH
VOH = 2.4 V, GROM_SDA, GROM_SCL
Condition
MIN. 2.0 -0.5 -6
TYP.
MAX. VDD+0.5 +0.8
Unit V V mA
Low-level output current
IOL
VOL = 0.4 V, GROM_SDA, GROM_SCL
6 10.0
mA
Input leakage current PCI interface High-level input voltage Low-level input voltage High-level output current Low-level output current Input leakage current Cable interface Differential input voltage
IL
VIN = VDD or GND
A
VIH VIL IOH IOL IL VOH = 2.4 V VOL = 0.4 V VIN = VDD or GND
2.0 -0.5 -2 9
5.5 +0.8
V V mA mA
10.0
A
VID
Cable input, 100 Mbps operation Cable input, 200 Mbps operation Cable input, 400 Mbps operation
142 132 118 1.165 0.935 0.523 172.0 1.665 1.438 1.030 -0.81 -4.84 -12.40
260 260 260 2.515 2.515 2.515 265.0 2.015 2.015 2.015 +0.44 -2.53 -8.10 7.5
mV mV mV V V V mV V V V mA mA mA V V
TpB common mode input voltage
VICM
100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling Cable output (Test load 55 ) 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling
Differential output voltage TpA common mode output voltage
VOD VOCM
TpA common mode output current
ICM
100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling
Power status threshold voltage TpBias output voltage
VTH VTPBIAS
CPS 1.665
2.015
Remarks 1. Digital core runs at 3.3 V. 2. PCI Interface can run at 5 or 3.3 V, depending on the choice of 5 V-PCI or 3.3 V-PCI. 3. All other I/Os are 3.3 V driving, and 5 V tolerant. 4. 5 V are used only for 5 V-PCI clamping diode.
5.0 V 3.3 V
Protection Circuit
I/O Buffer
32
Preliminary Data Sheet S15306EJ2V0DS
PD72874
AC Characteristics
PCI Interface See PCI local bus specification Revision 2.2. Serial ROM Interface See AT24C01A/02/04/08/16 Spec. Sheet.
Preliminary Data Sheet S15306EJ2V0DS
33
PD72874
6. PACKAGE DRAWING
120-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A B
90 91 61 60
detail of lead end CD S P T
120 1
31 30
R Q
L U
F G H I
M
J
K
S
N
NOTE
S
M
ITEM A B C D F G H I J K L M N P Q R S T MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.20 1.20 0.180.05 0.07 0.40 (T.P.) 1.000.20 0.50 0.17 +0.03 -0.07 0.08 1.000.05 0.100.05 3 +4 -3 1.20MAX. 0.25 P120GC-40-YEB
Each lead centerline is located within 0.07 mm of its true position (T.P.) at maximum material condition.
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Preliminary Data Sheet S15306EJ2V0DS
PD72874
7. RECOMMENDED SOLDERING CONDITIONS
The PD72874 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Table 7-1. Surface Mounting Type Soldering Conditions
PD72874GC-YEB: 120-pin plastic TQFP (Fine pitch) (14 x 14)
Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher). Count: three times or less Exposure limit: 3 daysNote (after that prebake at 125C for 10 hours) Partial heating Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row) -- Soldering Conditions Recommended Condition Symbol IR35-103-3
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Preliminary Data Sheet S15306EJ2V0DS
35
PD72874
[MEMO]
36
Preliminary Data Sheet S15306EJ2V0DS
PD72874
[MEMO]
Preliminary Data Sheet S15306EJ2V0DS
37
PD72874
[MEMO]
38
Preliminary Data Sheet S15306EJ2V0DS
PD72874
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Preliminary Data Sheet S15306EJ2V0DS
39
PD72874
EEPROM and Firewarden are trademarks of NEC Corporation. VGA is a trademark of IBM Corporation.
* The information in this document is current as of April, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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